In your design as the timer clock is at 1MHz, the timer count is going to overflow and restart from initial count. For 4KHz input clock this can happen upto 250 times. When we capture the old and new value before and after overflow, the measurement of old-new can be a spurious value. I am suspecting this to cause the issue.
Hello VRSR, thank you for your answer.
I'm not sure to understand it very well : what do you mean by 'the timer clock is going to overflow and restart from initial count.' ?
Can you explain a bit more?
Thank you, regards
I meant timer count. I have corrected previous response.
Vasanth R S
I'm not sure about your answer : at 1Mhz, the period of the timer clock is 1µs. At 4kHz, the period of the input signal is 250µs. The timer count will decrease by 250. When it overflows, the calculated value should be correct.
To see if the error comes from the overflow, I changed th number of bits of the timer to 32. The overflow will occur every 4295 s (more than on hour), but I still get the same spurious results .
Has anyone an idea of what happens?