System- and peripheral interconnect blocks are not a MPU.
PSoC6 TRM description describe below.
An MPU that is implemented as part of the bus infrastructure. This type is found in bus masters such as crypto and test
controller. The definition of this MPU type follows the ARM MPU definition (in terms of memory region and access attribute
definition) to ensure a consistent software interface.
Only three of the MPUs are usable for customers - MPU0 for CM0+, MPU1 for Crypto and MPU14 for CM4. The fourth MPU (MPU15) is meant for test controller, which is not usable for customers.
I see that is a mistake in our TRM document and will raise a defect ticket to get it rectified. Thanks for pointing it out.
Meenakshi Sundaram R