2 Replies Latest reply on Mar 28, 2018 1:11 PM by tugay.doner_3177296

    CY7C2663KV18 - 450BZI part pll turn off pin(DOFF)




      *CY7C2663KV18 - 450BZI has an internal PLL and that PLL is controlled via DOFF pin (pll turn off (active low)).

      * When this part selected in the Xilinx MIG IP, it generates a qdriip_dll_off_n pin.

      * In the MIG IP datasheet it is written that qdriip_dll_off_n pin turns off the internal DLL in the memory device.  What is the DLL ? This DLL is PLL in the part CY7C2663KV18 - 450BZI ? This part CY7C2663KV18 - 450BZI  does not contain any internal DLL, does it ?  If there is no internal DLL in the part CY7C2663KV18 - 450BZI, why Xilinx MIG IP generates this qdriip_dll_off_n pin  ? Or DLL and PLL is different things ? Should I connect these two pin to each - other, or not ?


      Best Regards,

        • 1. Re: CY7C2663KV18 - 450BZI part pll turn off pin(DOFF)

          Hi Doner,


          The part CY7C2663KV18 - 450BZI does not contain a DLL. It only has a PLL instead. Both PLL and DLL are used to obtain phase aligned signal with regards to a reference signal. One of the major difference between them is that a PLL extract both frequency and phase of the input signal whereas DLL extracts only the phase. This is due to the the fact that the PLL uses a VCO and DLL does not use them.  DLL and PLL may perform the same function - aligning data relative to the reference clock present at the receiver. However, the way the alignment is performed is different. PLL varies frequency, while DLL varies delay.

          Ideally you should not connect these two pins to each other, but if you do you may observe some performance issues.




          • 2. Re: CY7C2663KV18 - 450BZI part pll turn off pin(DOFF)

            Dear @prbd,


            I am planning to connect these two pins, after comparing timing requirements.


            Best Regards,