Interfacing iso. ADC like AD74XX

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
lock attach
Attachments are accessible only for community members.
Anonymous
Not applicable

Hi everyone,

I need to interface two isolated ADCs like the AD7403 from Analog Devices to the PSoC 5LP.

The ADC puts out a data stream of 1 and 0 and the average of this stream represents the analog value.

Of course a simple RC filter could be used to generate a moving average which could be samples by PSoC's ADC, but I was wondering if there is a more elegant solution to this.

At the moment I am running a single AD7403 at 5 MHz (the lowest possible frequency).

The digital output of the ADC is acquired by a status register.

A DMA then transfers the data to the digital filter block where I use a SINC4 low pass filter.

This way I am creating single byte transfer requests at 5 MHz on the DMA.

So far it seems to be working fine but I have not checked the integrety of the data.

Can the DMA really handle such a frequency?

I need to interface two of those ADCs and possibly at higher frequencies (10 MHz each) - do you think my solution is viable for such an application?

Is there an alternative?

I attached a small example in PSoC Creator and the datasheet of the AD7403

Thank you

0 Likes
1 Solution
HeLi_263931
Level 8
Level 8
100 solutions authored 50 solutions authored 25 solutions authored

The recommended way is to use a sinc-filter on the incoming bitstream (I think there is an app note for the AD7403 detailing that). What you also can do is e.g. collecting e.g. 64k pulses and count how many of these are 1s. I did this as a test project and can confirm that it works. Disadvantage is that you get a slower response than using a digital filter.

View solution in original post

0 Likes
7 Replies
HeLi_263931
Level 8
Level 8
100 solutions authored 50 solutions authored 25 solutions authored

The recommended way is to use a sinc-filter on the incoming bitstream (I think there is an app note for the AD7403 detailing that). What you also can do is e.g. collecting e.g. 64k pulses and count how many of these are 1s. I did this as a test project and can confirm that it works. Disadvantage is that you get a slower response than using a digital filter.

0 Likes
Anonymous
Not applicable

Hi,

thanks for the replay!

A counter sounds pretty straightforward indeed.

I suppose I can trade accuracy for bandwidth (and vise versa) when I adjust how many pulses I count.

Thanks

0 Likes
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Martin,

one way of averaging 1-bit input is to use a custom LPFilter component, which is simple first-order exponential filter. See example project here:

http://www.cypress.com/comment/377701

Instead of using internal ADCs, just set Filter input bus width to a single bit, and attach it to the AD7403 output. The Filter output is an exponentially-averaged bitstream at lower rate. You can further average it by using PSoC digital Filter. For example, starting with ADC rate of 20MHz, and Filter dumping length 256, the decimated output will be 4-bit at rate of ~80kHz, which can easily be filtered further by the PSoC Digital Filter.

It is possible to cascade several LPFilter components to make a higher-order filter, depending on strobe frequency and other PSoC resources. Simplest way to transfer data to DFB is to read LPFilter output directly using API (for lower speed); to use DMA attach a Status Register and use StatusReg-DMA-DFB transfer.  

/odissey1

ADC_SAR_LPF_2x_01.png

0 Likes
lock attach
Attachments are accessible only for community members.
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Martin,

Attached is an example of the bitstream integration using LPFilter component. To simulate ADC bitstream it uses a PriSM component, which pulse density is being varied using rotary encoder. The bitsream first aggregated using LPFilter and decimated to lower data rate, acceptable to the digital Filter component. The data is displayed using the Multichart plotting SW. Project uses approx 30% of PSoC5 resources, indicating that sampling of two bitstreams simultaneously is feasible at about 20MHz rate.

Project files are attached.

Other libraries needed to operate the project:

Quad Decoder with Button Switch component for rotary shaft encoders

Annotation library for CY8CKIT-059 Prototyping Kit

/odissey1

LPF_bitstream integrator_01a.png

0 Likes
Anonymous
Not applicable

Hello odissey1,

thank you for the answer.

The LPFilter seems to be a very usefull component - not just for single-bit bitstreams!

Why are such usefull things not included in PSoC Creator?

The date on the datasheet says "Revised August 21, 2016".

Thanks for your support.

0 Likes

Martin,

The LPFilter is so-called "Community component". You can find some of those on this (old) page

http://www.cypress.com/validated-components

I had no time to "release" the component - other things took a priority. Its main goal was to compliment ADC_SAR_ex digital bus output (8-12-bits). It can be used for a single bitstream averaging as well, but there are also several other tools available for that. As mentioned above, a standard Counter can be used as a simple FIR-filter. Thee are also other community components by Chris Keeser (KEES) for that, namely Bitstream Integrator and Sinc^2 filter. I will try to check those and/or post a links to those examples.

/odissey1

P.S. The DMA settings (StatusReg-DMA-Fillter) in your project are incorrect, please find correct DMA settings in the DMA.c file above.

Links:

http://www.cypress.com/forum/psoc-community-components/udb-single-bit-8-bit-iir-filter

UDB 2nd Order Cascaded Integrator Comb (CIC) Decimator. Pairs very nicely with the SC/CT DelSig mod...

0 Likes
lock attach
Attachments are accessible only for community members.

Martin,

Here is another example of DelSig_ADC filtering using second-order CIC Decimator (AKA Sinc^2 filter). The Delta-Sigma bitstream is produced by the Switched Capacitor modulator (SC_Modulator), both components are made by the Chris Keeser (KEES). To use with external ADC, the Modulator is not needed.

Links to the original forums:

UDB 2nd Order Cascaded Integrator Comb (CIC) Decimator.  Pairs very nicely with the SC/CT DelSig mod...

SC/CT block first order DeltaSigma modulator

The bitsream from Modulator is first filtered to about 10-bits and decimated by the Decimator component to lower data rate (approx. 1/120 of sampling clock), and then passed to the digital Filter by DMA. The data is displayed using the Multichart plotting SW. Project uses approx 16% of PSoC5 resources with max BUS_CLOCK of about 55MHz.

Notice that unlike the Filter component (above), which was able to sample a bitstream at ~30MHz data rate, the Decimator requires several bus clocks (up to 😎 to sample the input. This will limit ADC sampling clock to about 5-6MHz (6MHz x 8 = 48 MHz BUS_CLOCK). Another difference is that the exponential Filter is 1-st order IIR filter  written entirely in Verilog, and Sinc^2 is 2-nd order FIR filter utilized in UDB Datapath.

The project has not been tested at maximum sampling rates, as Modulator is limited to 4 MHz maximum. With external ADC's there might be some bottlenecks with Decimator and digital Filter, so watch out!

/odissey1

Project files and libraries are attached (the SC_Modulator is cosmetically updated from the original).

Other libraries needed to operate the project:

Quad Decoder with Button Switch component for rotary shaft encoders

Annotation library for CY8CKIT-059 Prototyping Kit

KEES_Decimator_02a.png

0 Likes