1 Reply Latest reply on Mar 9, 2018 2:49 AM by prbd

    ASYNC SRAM layout


      Hi to all,


      We are going to use a STM32F2 with a async SRAM CY7C1041GN30-10ZSXI.


      It is the first time I work with one of these and I have many many questios: trace lengths should be similar, impedance controlled .....


      Do you know any document where I can get the answers for these questions and more tips to take into consideration?


      Thanks in advance,