6 Replies Latest reply on Mar 9, 2018 12:34 AM by kubo_2493671

    EOC status bit

    kubo_2493671

      In ADC_SAR.c, why dose ADC_SAR_IsEndConversion() call CyDelayUs(1u) ?

       

      I don't understand the meanig of comment /* wait one ADC clock to let the EOC status bit release */.

      And, I can't find the detail of EOC status bit.

        • 1. Re: EOC status bit
          vsrs

          Hello Fumio san,

           

          The EOC status bit will be updated by the SAR sequencer block. So when we try to access the register using the API, the CPU should wait for the register to be released by the sequencer block.

           

          Best Regards,
          VSRS

          • 2. Re: EOC status bit
            kubo_2493671

            Thank you for your prompt reply.

             

            I've read the component datasheet ADC_SAR_Seq 2.10.
            So, I understood the behavior of EOC/EOF status bit.

             

            And, I have one more question.

            Can I check the eoc signal condition directory by API or my firmware without an interrupt?

             

            Best Regards,
            Fumio Kubo

            • 3. Re: EOC status bit
              vsrs

              Hello Fumio san,

               

              Yes you an do the same register address as used in the ADC_SAR_IsEndConversion() API. Remember the register is cleared on read. Polling for the result might delay other activities of the CPU.

               

              Best Regards,
              VSRS

              • 4. Re: EOC status bit
                kubo_2493671

                Thank you for your reply. I understood how to use ADC SAR (Seq).

                 

                So, I will make my system design using "1 x ADC_SAR_Seq" and "4 x PGA".
                "4 x PGA" inputs are for 4 external sensors.

                 

                But, Only GPIOs can be connected to ADC_SAR_Seq inputs. PGAs outputs can not be cennected to these.

                Could you teach me this reason?

                 

                Best Regards,
                Fumio Kubo

                • 5. Re: EOC status bit
                  vsrs

                  Hello Fumio san,

                   

                  You should be able to connect PGA output to SAR ADC input. If any routing failure is happening, that might be due project complexity or some other reason. One more thing if your doubts are different from the previous one, it is always better to create a new thread. This will help others with the same doubt to find the right answer by searching.

                   

                  Best Regards,
                  VSRS

                  • 6. Re: EOC status bit
                    kubo_2493671

                    I appreciate your adivce.

                    I will ask my question on a new thread.

                     

                    Best Regards,

                    Fumio Kubo