So I'm currently using the SlaveFIFO firmware for the FX3 to send and receive 32 bit data packets from a Master FPGA. Each transaction involves a packet sent from the PC software then once read by the FPGA determines how many 32 Bit words should be returned. As the number of words returned is variable, I have been using Pktend to reduce the latency in the over all transaction, and this is where my problem lies (my buffer size is 16k and only 1 DMA buffer).
If in the first transaction the PC software requests a set amount of words, lets say 40, the FIFO transaction will work fine. However if in the next transaction the PC software requests any more words than previously requested, like 41, then the transaction will fail, and Xferdata will return false to the Bulk In Endpoint. So far I've tracked it down to the FX3 firmware, whether its in the GPIF or actual firmware I'm unsure.
Please let me know if I can provide any other helpful information
1. How much amount of data that you are requesting over BULK IN Endpoint in host application in 40 word case and 41 word case?
2. On what basis you control the PKTEND signal? What is the status of SLWR when you assert the PKTEND.
3. What is your GPIF State Machine?