It seems the output and the input will be same.
## I want to make an output value (1'b1)for posedge and another output (1'b0) for negedge of same clock .
This can done by using;
always @ (posedge inp_sig)
out1 = 1'b1;
But when the first output should go to zero? if it is on negedge of the input signal, you are just generating 3 signals which are same as the input.
Please elaborate the requirement with an example [input/output signal diagram]