1 Reply Latest reply on Feb 27, 2018 9:55 PM by jobi

    using posedge and negedge of clock in same always block

    shoukiabdlkalam_2746976

      HI

      In my Verilog  program using PSOC I want to make an output value (1'b1)for posedge and another output (1'b0) for negedge of same clock .and these two output should come to same output continuously(like 1010101010). is this possible????

        • 1. Re: using posedge and negedge of clock in same always block
          jobi

          Hi,

          It seems the output and the input will be same.

          ## I want to make an output value (1'b1)for posedge and another output (1'b0) for negedge of same clock .

          This can done by using;

          always @ (posedge inp_sig)

          begin

          out1 = 1'b1;

          end

           

          But when the first output should go to zero? if it is on negedge of the input signal, you are just generating 3 signals which are same as the input.

          Please elaborate the requirement with an example [input/output signal diagram]

           

          Jobin GT