Doing this in hardware seems impossible. It's difficult enough to build new 8-bit items in Verilog, and for most encryption you are dealing with 128 bits or more.
Why would you want to do this in hardware?
Here's a C library for AES. This should work in software for PSoC 5. GitHub - kokke/tiny-AES-c: Small portable AES128/192/256 in C
thank you for the link, I'll try that. Reason for hardware implementation was that I don't know how much time a PSoC 5LP needs to do AES. With the code from your link I can do some performance measurements.
Can you share me some information about how to measure the performance and making Hardware AES on PSoC 5LP.
Hardware AES will be unfeasible I think. I have personally implemented software AES on PSoC 5LP systems and the performance hit was fairly significant, but not unusable. I implemented a bootloader that performed firmware upgrades in the field from AES encrypted bootloadables. I had to change the CPU frequency to the maximum in the bootloader in order to have the decryption take place in a reasonable amount of time. If you are only needing to decrypt small amounts of data, it may not be a big deal. I was decrypting full hex rows for very large firmware files. It is doable but performance will obviously suffer to some extent.
I am new on cypress. I have AES-CBC code and I would like to test the performance and cost(time, powerconsumption) on PSoC 5LP. If you do not mind, can you share the document or link how to test those performance? I saw some guys did it, but I could not find any tutorial or document.