I will be easier for the community to help you if you share your project (just make a minimal archive of your project with PSoC Creator).
Could you share your project?
A topic with a similar problem (interrupt not occurred with dual application) reveals that : "The reason for this fix is that the vector table on the CM4 must be 0x400 aligned."
You check this point.
I have now attached the project to the original message.
Use CE216795_DualCoreSharedMemory01.cyprj as the project file.
Some more information:
When I manually set IPC_INT_1 to PENDING [ NVIC->ISPR |= 0x400; ], I do manage to stop with the debugger at the Default_Handler in CM4.
It means that the interrupt table is ok, and the interrupt itself is enabled.
Still, when using IPC to trigger the same interrupt, the debugger won't stop on the Default_Handler, that is, the interrupt is not really triggered.
According to the INTR_MASK register, the notification has passed to CM4, and the mask is enabled.
Any clue would be great
I have written program where CM0+ trigger interrupt in CM4 using IPC notify and sends pointer, while CM4 after reading pointer trigger interrupt in CM0+ using IPC release.
Let me know if this helps.
You could also use the IPC Pipes or Semaphore layer APIs that comes with the PDL.
This layer makes very easy to handle synchronization and messages between the cores.
We are creating a code examples to show off how to use them. From now, you can refer to the PDL documentation.