Just like FTDI FT600Q-FT601Q(USB 3.0 to FIFO Bridge).
Is that possible to configure FX3 to receive video stream from Host, and then output parallel data via GPIF II.
Design GPIF to support : ((Parallel FIFO bus clock / Control signal / data bus output)
- output Pixel clk
- output FV( Vsync )
- output LV( Hsync )
- output Data bus (8 ~16bits)
Such an implementation may sound feasible, but there may be many issues in practical realization. This has not been tested before. The FV, LV synchronization on the GPIF lines with respect to the lines and frame ending is not possible to achieve with accuracy.