Such an implementation may sound feasible, but there may be many issues in practical realization. This has not been tested before. The FV, LV synchronization on the GPIF lines with respect to the lines and frame ending is not possible to achieve with accuracy.
Yes its possible. We have supported a customer to design a MIPI based secondary display through USB. This design had a vendor driver in the Host PC, FX3 device connected to parallel to MIPI bridge and a MIPI to MIPI bridge to control the frame rate, brightness, etc. of the MIPI display.
As Madhu said, the rate matching has to be done and this is done by the MIPI to MIPI bridge. FX3 can generate the FV, LV signals but the clock signal will be derived from FX3 SYS_CLOCK (~400MHz) through dividers and this clock value may or may not serve the purpose.