The problem: The LED2472G supports a "quasi" SPI protocol. In addition to the MISO, MOSI and SCLK lines I have to a manage an LE line. This LE (latch enable) line needs to toggle high for a precise amount of clock cycles during a data transfer.
I've tried approaching this two ways:
1) "Bit bang" the SPI protocol using a timer to have finer control of the LE relative to the clock cycles. This works but it's not desirable, I'd rather manage this using internal hardware.
2) A PWM that manages both the LE line and an SPI component (driven with DMA): The PWM's compare interrupt triggers the initial SPI write. Later the PWM's terminal count interrupt toggles the LE line. Unfortunately the LE doesn't always toggle high at the correct time relative to the SCLK.
Is there an approach I haven't considered? Could I somehow modify a hardware component to support an LE line?