Provided below is a custom implementation of analog Phase-Locked Loop (PLL_scm).
Component implements Phase-Frequency Detector (PFD) as phase comparator and voltage-controlled oscillator based on switched-capacitor delta-sigma modulator. Only few external capacitors and resistors required for low-pass filter. PLL_scm can lock to digital signal, producing one output of the same frequency, and another one of multiplied frequency, both are phase-aligned with the input. The component was designed to operate at low frequencies (10Hz–10kHz), with primary goal of tracking AC power lines (50-60 Hz).
Component was developed as part of RMS detection project. It can be useful for frequency multiplication, quadrature generation, motor control, guitar sound effects, etc.
It was tested using CY8KIT-059 PSoC5 prototyping kit. Several demo projects are provided.
Component Major features:
Implements analog PLL using Type-II Phase Frequency Detector.
Uses 1st-order delta-sigma modulator as VCO.
Primary output is locked in both frequency and phase.
Secondary output for multiplied frequency.
Output for optional lock detection.
Does not consume CPU.
Attached archive contains component library, component datasheet and several demo projects for PSoC5. Please read installation instructions in the readme.txt.
The component provided as-is, no liabilities. It is free to use and modify.
YouTube video showing component in action:
Figure 1. Project schematic using 3-rd order LPF.
Figure 2. O-scope snapshot: blue trace - PLL input (60Hz), yellow trace - PLL output (locked).