2 Replies Latest reply on Aug 4, 2018 7:22 PM by user_342122993

    custom Phase-Locked Loop (PLL) implementation using PSoC5

    user_342122993

      Hi,

       

      Provided below is a custom implementation of analog Phase-Locked Loop (PLL_scm).

       

      Component implements Phase-Frequency Detector (PFD) as phase comparator and voltage-controlled oscillator based on switched-capacitor delta-sigma modulator. Only few external capacitors and resistors required for low-pass filter. PLL_scm can lock to digital signal, producing one output of the same frequency, and another one of multiplied frequency, both are phase-aligned with the input. The component was designed to operate at low frequencies (10Hz–10kHz), with primary goal of tracking AC power lines (50-60 Hz).

       

      Component was developed as part of RMS detection project. It can be useful for frequency multiplication, quadrature generation, motor control, guitar sound effects, etc.

      It was tested using CY8KIT-059 PSoC5 prototyping kit. Several demo projects are provided.

       

      Component Major features:

         Implements analog PLL using Type-II Phase Frequency Detector.

         Uses 1st-order delta-sigma modulator as VCO.

         Primary output is locked in both frequency and phase.

         Secondary output for multiplied frequency.

         Output for optional lock detection.

         Does not consume CPU.

       

      Attached archive contains component library, component datasheet and several demo projects for PSoC5. Please read installation instructions in the readme.txt.

       

      The component provided as-is, no liabilities. It is free to use and modify.

       

      YouTube video showing component in action:

      Custom Phase Lock Loop (PLL) demo using PSoC5 microcontroller - YouTube

       

      regards,

      odissey1

      PLL_scm_01d_01b.png

      PLL_scm_locked 60 Hz.jpg

        • 1. Re: custom Phase-Locked Loop (PLL) implementation using PSoC5
          jorgesilva

          Is it possible to input a 32,768kHz clock (DS3231) and get 1,048576MHz (32x32,768) to use with DDS32?

          • 2. Re: custom Phase-Locked Loop (PLL) implementation using PSoC5
            user_342122993

            jorgesilva,

            1 MHz is too high for this type of PLL. The component uses very specific VCO, based on Delta-Sigma Modulator, which is optimized for low frequency operation (<100kHz).

             

            I see several options to get to 1.048576 MHz.

            1. Use XTAL (24 MHz) or external clock as stable reference, and DDS32 component to obtain desired frequency with accuracy of about 0.01 Hz. This is not true lock though. See #15 at

            DDS24: 24-bit DDS arbitrary frequency generator component

             

            2. It is possible to modify PLL component using a different type of VCO, optimized to operate in 1 MHz range. Basically, use PFD schematic and divider and add your own VCO. I tried several VCO schematics and was able to get up to 30 MHz, but had no time to put it together as a component. Your advantage is that desired frequency range is very narrow, so you can use simple 1 MHz ceramic resonator +2 capacitors, plus a varactor diode to tune oscillator frequency within ~1% to lock to 32x32768 Hz quartz. See example picture.

             

            VCO_varicap_ex.png   

            3. As purely theoretical approach, there should be a way to lock PSoC5 main PLL to 32kHz quartz directly. I have not accomplished that, but think it is possible with some trickery.

            /odissey1

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