ADC optimized power strategie

[KrDe_284951]

Hi,

In a battery operated system I want to sample an analog sensor with a sample rate of 10Hz (the ADC conversion time may be taken a lot shorter. The internal conversion freq must probably be set as high as possible to be optimze for processor sleep time) in a 'continuous' mode. In order to keep the over all power consumption to a strcit minimum I'm looking for an optimal stategy to perform this task. (For reason of simplicity, you can disregard all other features that may or may not be running on the processor). Targeted average processing power is preferably as less as 20µA.

Many thanks in advance for your ideas on this subject.

Kris

[EmHo_296241 · Accepted solution]

Hey,

This might be helpful for power reduction strategies<http://www.cypress.com/file/121271/download >. If you want strict timing, think about reducing the acquisition time by checking architecture TRM, if averaging is done you can remove that(trade of with accuracy). You can check for the end of conversion and initiate sleep.