4 Replies Latest reply on Feb 3, 2018 4:41 AM by bob.marlowe

    verilog related doubts.

    jaseelaka945_2746661

      Helloeveryone

               I created verilog component (squarewave generator) and i dragged it and kept in the Topdesign from default tab .If i want to see the output i should give inputs to the component , my inputs are clock, enable.if enable =0 counter start counting otherwise counter stop counting. how to give 1 and 0 to enable pin in topdesign. anyone please help me.

       

       

       

      my topedesign

       

       

      topdesign.PNG

      `include "cypress.v"

      //`#end` -- edit above this line, do not edit this line

      // Generated on 01/31/2018 at 21:29

      // Component: clkgeneration

       

      module square_wave(clk,enable,clkout);

         input clk; // assuming 4 KHz

         input enable;

         output reg clkout;

         reg [11:0]  counter; // 12-bit for numbers up to 3999

       

       

         always @(posedge clk)

           begin

              if (enable == 1'b1  ||  counter == 12'd3999) // period, count from 0 to n-1

                counter <= 0;

              else

                counter <= counter + 1'b1;

       

       

              // synchronous output without glitches

              if (enable == 1'b0  &&  counter < 12'd2000) // duty cycle, m cycles high

                clkout = 1'b1;

              else

                clkout= 1'b0;

            end

      endmodule // square_wave