4 Replies Latest reply on Jan 26, 2018 6:45 AM by paul.chambre_1977636

    If a buffer component needed for fanout issues?

    paul.chambre_1977636

      I'm running into odd problems with my design when I add extra gates to be driven from GPIO Pins. It looks sort of like a fanout issue. For instance, I have a R/W pin (low for write). It's a CMOS level Digital Input in my design. The solution works fine if this signal is connected to an AND gate input or a NOT input, but not if connected to both. I added a second NOT in series, so that the output from the first NOT could drive the AND gate (the pair acting like a buffer), and everything works again. It looks, in the case, like the extra load of both a NOT and an AND is too much for this R/W signal.

       

      I would have thought, though, that the Pins themselves would act as buffers. There is actually an Input Buffer setting on the Input tab, and it is enabled.

       

      There also is no buffer component in the palate, which again makes me think they should be needed.... but then why am I seeing this kind of behavior. I saw something similar when I connected another Digital Input pin to both a Status Register and a NOR gate. One or the other works, but not both.

       

      This is on a CY8C5888.

       

      Thanks,

      Paul