I2c transmitting issue

Hello Bob,

Thanks for response,

I got to know that NAK is required by psoc 4 device when Master receives last byte,

Should I read until 255 that means Overflow condition occurs in psoc 4?

should the i2c Rd pointer be cleared when Overflow condition occurs in psoc 4

Issue in reading at pic controller from psoc4 device is  iam reading old values from TX fifo register when latest values to be read at pic controller side,

Please clarify on this issues.

Thanks and regards,

Pramod Kashyap,

Hello Bob,

Thanks for response,

That means after reading required number of bytes at master we need to send NAK from master to slave,

As iam able to read 255 at master side from psoc4,

That indicates Overflow has occurred at psoc4.

I will try to reset all the buffer at psoc4.

Thanks and regards,

Pramod

Hello Bob,

How can i Avoid the Overflow condition from been executed after all the data bytes are been transmitted to Master controller,

as i might be transmitting 2 bytes data max to master controller,

I have below code snippet generated by PSOC creator for I2C driver of PSOC 4 device,

         /* I2C_INTR_TX_EMPTY:

            * The master reads the slave: provide data to read or 0xFF in the case of the end of the buffer

            * The overflow condition must be captured, but not set until the end of transaction.

            * There is a possibility of a false overflow due to TX FIFO utilization.

            */

            if(I2C_CHECK_INTR_TX_MASKED(I2C_INTR_TX_EMPTY))

            {

                while(I2C_I2C_FIFO_SIZE != I2C_GET_TX_FIFO_ENTRIES)

                {

                    /* Temporary slRdBufIndexTmp is used because the master can NACK the byte and

                    * index roll-back is required in this case. The slRdBufIndex is updated at the end

                    * of the read transfer.

                    */

                    if(I2C_slRdBufIndexTmp < I2C_slRdBufSize)

                    /* Data from buffer */

                    {

                        I2C_TX_FIFO_WR_REG = (uint32) I2C_slRdBufPtr[I2C_slRdBufIndexTmp];

                        I2C_slRdBufIndexTmp++;

                    }

                    else

                    /* Probably Overflow */

                    {

                        I2C_TX_FIFO_WR_REG = I2C_I2C_SLAVE_OVFL_RETURN;

                        if(I2C_slOverFlowCount <= I2C_I2C_TX_OVERFLOW_COUNT)

                        {

                            /* Get counter in range of overflow. */

                            I2C_slOverFlowCount++;

                        }

                    }

                }

                I2C_ClearTxInterruptSource(I2C_INTR_TX_EMPTY);

            }

in the bold part of the code snippet is overflow condition,

Please can you clarify on this issue ASAP.

Thanks & Regards,

Pramod Kashyap

Hello Bob,

As per the previous Code snippet from I2C generated code for PSOC4,

I have few querries,

1) How can i synchronise the Reads from PSOC4 device, as iam not able to consistently observe values at PIC master controller.

2) How can i ACK the transmits to Master after every read from  PSOC4 device?

Please find below the code snippet for master controller end,

uint8_t returnbuff()

{

    uint8_t buff[9]={0,0,0,0,0,0,0,0,0};

    uint8_t data;

    I2CReadBuff(I2C_SLAVE_ADDR, cmd, buff, 9);

   data = buff[0];

   return data;

}

Iam seeing sometimes wrong values at buff[0] other than expected values.

Please help me on this issues ASAP.

Thanks & Regards,

Pramod Kashyap

Hi Bob,

Thanks for response,

I gave  nack from master to psoc4,

Should slave send any ack signal to master??

How can avoid Overflow condition being executed in psoc4 controller.

Thanks and regards,

Pramod Kashyap

Hi Bob,

Iam still facing issues if i do NACK from Master controller,

Iam not able to read the proper data's at required buffer place at  PIC master controller ,

Below is my code snippet for master controller, please can you help me if this sequence is alright,

    I2C1CONbits.I2CEN = 1;                               Enable I2C

    I2CStart();                                                      Start bit

    I2CSendByte(addr);                                       Address with Write command

    I2CSendByte(reg);                                         Cmd register 

    __delay_us(10);

    I2CRestart();                                                  restart

    I2CSendByte(addr | I2C_READ_BIT);           Address with Read command

    if (size > 0) {

        for (i = 0; i < (size-1); i++)

            I2CReadAck(buff++);                             Copying the Array from Receive buffer

    }

    I2C1CONbits.ACKDT = 1;                              NACK signal

    I2C1CONbits.ACKEN = 1;                              Enable NACK.

    I2CReset();                                                      STOP Condition

    I2C1CONbits.I2CEN = 0;                                Disable I2C

Please let me know if this is correct?

THanks

Pramod

Hello Bob,

Thanks for reply,

I have checked the NAK handler in slave controller is getting triggered after i enable NAK at master controller.

Please find below snippet of code where iam updating the read buffers at slave controller as i get the command from Master,

        case cmd1:

         u8i2cReadBuffer[ZERO] = 10;

          break;

        case cmd2:

        u8i2cReadBuffer[ZERO] = 20;

         break;

        case cmd3:

        u8i2cReadBuffer[ZERO] = 30;

        break;

        case cmd4:

        u8i2cReadBuffer[ZERO] = 40;

         break;

Iam sending back to back read commands from PIC master controller to PSOC controller,

Is the above way of updating to read buffer is right, as iam updating to single location of read buffer.

How can clear the TX FIFO in psoc4 controller.

please can you clarify on this issue.

Thanks & Regards,

Pramod Kashyap

Hi Bob,

Thanks for response,

Can you please let me know how can i clear the previous Read buffer values in slave,

Iam observing that Read buffer at index 0 hold previous data even after sending NACK,

Iam also seeing that NACK handler is getting executed.

Please can you let me know on this issue.

Thanks & Regards,

Pramod