Please check if the FX3 i/p clock / crystal meets our specifications.
The MCLK can accept i/p from an external source, but the registers need to be configured.
The GCTL_I2S_CORE_CLK register has a bit that deciedes whether MCLK is input or output. (Please refer to the FX3 TRM).
This bit has to be set in the firmware *(uint32_t *)(0xE0052034) |= 0x4000000
This has to be done before the I2S Init function. As this feature has not been tested internally, please create a Tech Support case in case you face any issue with this.