1 Reply Latest reply on Feb 3, 2018 10:15 PM by madhul_36

    I2S MCLK and WCLK Not precise



      I configured the I2S with following properties


          /* Configure the I2S interface. */

          CyU3PMemSet ((uint8_t *)&i2sCfg, 0, sizeof (i2sCfg));

          i2sCfg.isMono = CyTrue;

          i2sCfg.isLsbFirst = CyFalse;

          i2sCfg.isDma = CyTrue;

      #if 1

          i2sCfg.padMode = CY_U3P_I2S_PAD_MODE_NORMAL;


          i2sCfg.padMode = CY_U3P_I2S_PAD_MODE_CONTINUOUS;



          i2sCfg.sampleRate = CY_U3P_I2S_SAMPLE_RATE_44_1KHz;

          i2sCfg.sampleWidth = CY_U3P_I2S_WIDTH_16_BIT;

          status = CyU3PI2sSetConfig (&i2sCfg, NULL);


      If padMode is CY_U3P_I2S_PAD_MODE_NORMAL , even though I set sampling rate as 44100 Hz, the WCLK comes as 44365Hz and MCLK as 11.3578MHz.


      Similarly, if padMode is CY_U3P_I2S_PAD_MODE_CONTINUOUS, even though I set sampling rate as 44100 Hz, the WCLK will be 44056Hz and MCLK as 5.63920 MHz.


      Why the WCLK is not coming precise 44100 Hz in either case? Does a change in the WCLK cause noise in the audio output? I am currently hearing periodic click noise in

      CY_U3P_I2S_PAD_MODE_CONTINUOUS and hissing noise in CY_U3P_I2S_PAD_MODE_NORMAL.


      I have read the I2s MCLK shall be 11.2896MHz to get 44100 Hz as sampling frequency (WCLK) as MCLK = 256x WCLK.