0 Replies Latest reply on Jan 12, 2018 2:04 AM by valentinec_2982031

    Access to fx2lp fifo buf.


      Hi everyone!


      I have fx2lp chip. My application is high speed parallel 8-bit ADC. I want to use full size of fifo (4k). I started from configuring GPIF master mode and have succeseful read buffer with 4*1024 isochronous transactions. Ok. Next step, that i want to realise is dump of fifo buffer to external i2c eeprom, but i have some problem with fifo reading. As says on TRM 8.5: "The CPU can only access the ‘active’ buffer of a multiple-buffered endpoint..." at this point i try to write-read 4k of test data to fifo from 8051 chip without GPIF as follow:


      1. set autopointer to 0xF000

      2. write 1024 bytes of "0x11" to buf and commit packet 1

      3. set autopointer to 0xF000

      4.  write 1024 bytes of "0x22" to buf and commit packet 2


      and i see in cyusb_linux window 4 iso transactions each contains 1024 bytes of test data 0x11..., 0x22.., 0x33..., 0x44... and this ok, but when i try to read from fifo with autoponters and dump to eeprom this contents i see 4 arrays with 1024 bytes with only 0x11 data, that means "active" fifo buf not switching while read and i see data from first part of fifo buf from 8051. Config of EP2 is IN, iso, 4x buf, 1024 size (config 12), fifo wordwide is 8bit.


      So my questions is next:

      1. Is the fifo - separate register memory which maps to RAM partialy (1024 bytes depending on the EP config)?

      2. How to make read of all parts of fifo buf?


      Desired application is: on interrupt fill 4k fifo from adc-> send to usb host(maybe not!)->and dump fifo contents to i2c eeprom.

      Please help to understand fifo read-write process!


      Best regards, Valentin.