1 Reply Latest reply on Jan 19, 2018 2:27 AM by vsrs

    Unobvious description of PWM

    user_447480723

      Hello. It is not obviouse the description and behavior of the left align ff pwm.

      First question is swap. Is it just shadow register or it is individual register ?

       

       

      In case of COMPARE_BUF is shadow register my expecting is :

      1. write in COMPARE_BUF will replace the value in COMPARE_BUF. Value in COMPARE will remain the same.

      2. every SWAP on TC will copy value from COMPARE_BUF into COMPARE. At this moment we will have the same value in COMPARE and COMPARE_BUF

      So DMA can write data into COMPARE_BUF and TC event will copy value from COMPARE_BUF into COMPARE and pwm will use COMPARE (every time copied from COMARE_BUF)

       

       

      In case of COMPARE_BUF is individual register my expecting is :

      1. write in COMPARE_BUF replace the value in COMPARE_BUF. Value in COMPARE will remain the same.

      2. on every SWAP the COMPARE and COMPARE_BUF will be "switched" so "current active logical compare register" will be switched from COMPARE to COMPARE_BUF and vice versa next time. The values in COMPARE and COMPARE_BUF will be different. The next SWAP will switch pointer from current COMPARE_BUF to COMPARE without coping one to another.

      So DMA should write one time into COMPARE, next time into COMPARE_BUF, next again in COMPARE and so on.

       

      What is right ?

       

      Second question is updating in runtime of COMPARE without of using SWAP.

       

       

      TCPWM datasheet says about double buffering. What does it mean ? Just COMARE and COMPARE_BUF or we have shadow registers ? Where can I read about it ? How does it work ? I've been looking for this in TCPWM datasheet, in PSoC 4 architecture reference manual and in PScC 4 registers reference manual. Have no answers.

       

      Compare event trigger DMA to send data into COMPARE register. Does COMPARE register realy take new value from DMA or data from DMA take place in an shadow register (double buffer) ?

      According to documentation COMPARE and PERIOD registers will be updated only on TC event. Ok. I will write PERIOD and COMPARE but they will be updated during next TC. Where in this case the new values of PERIOD and COMPARE are preserved ? As I understand the old values remain the same until TC event. But why I cannot write new value in PERIOD if it less then old value ? Until TC the PERIOD will not be changed but I cannot write it becase ... I do not have detailed information what going on in COMPARE and PERIOD after changing it's data on the run.

       

       

      I need to change COMPARE and PERIOD on the fly but have no detailed information about algorithm of it. Timers of STM32 much more complex but very predictable in every details. The main problem is documentation. Is not detailed.

        • 1. Re: Unobvious description of PWM
          vsrs

          Hello Krisanov,

           

          Please check the component datasheet PWM section

           

          So on terminal count the values of these registers are being exchanged. This is shown as an image too.

          So you can update the COMPARE_BUF value so that it will be come into effect on next TC.

           

          Best Regards,
          VSRS