thanks for your help!
The AN page 14 is about multiple Clocks. I cant see the Problem im my schematics. I use only one clock for all components.
At 48MHz there is no warning.
STA warnings , if you open the timing.html of your project you will find the Setup path /violations listed in the project .If you click on them you can see the complete path ,delay contributed by each path and the slack.
if the the slack is negative , you cannot operate the Bus Clk at the set freq, min would be 67 MHz to avoid any STA warnings and issues.
The reason there are STA warnings are because of the Double sync option set in the input pins to the UART component, if you make them transparent, you do not have STA contraints any more.
This is because ,the Synchronization at the pin level is with BUS clock and the delay in UART path cannot meet this timing.
So you can either reduce the BUS clk or change the input UART pins to transparent mode(Double click pin-->Pins-->Input-->Sync mode).
The latter should not have any issues.
If you are concerned about noise ,use good oversampling and 2 out of 3 polling methods.
i lowered the oversampling from the UARTs from x16 to x8 and switched the Timer from 16 bit to 8 bit. Then it works up to 77 MHz PLL.