4 Replies Latest reply on Jan 4, 2018 3:36 AM by user_395531908

    How get i rid of setup time violation warnings

    user_395531908

      Hello Forum,

       

      i built an DMX-Merger with the PSOC5LP Kit (3 DMX Inputs and 1 DMX Output).

      Now i want to setup the clocks as fast as physics allow.

       

      But i get a warning: Warning-1366: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( Clock_1 ).

       

      What is the best performance that i can get?

       

      Günter

       

      Static Timing Analysis

      Project : Psoc5test
      Build Time : 12/28/17 18:54:54
      Device : CY8C5888LTI-LP097
      Temperature : 0C - 85/125C
      VDDA : 5.00
      VDDABUF : 5.00
      VDDD : 5.00
      VDDIO0 : 5.00
      VDDIO1 : 5.00
      VDDIO2 : 5.00
      VDDIO3 : 5.00
      VUSB : 5.00
      Voltage : 5.0

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      - Timing Violation Section

       

       

      Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.

       

      ViolationSource ClockDestination ClockSlack(ns)
      Setup
      CyBUS_CLKClock_1-7.508

      - Clock Summary Section

      ClockDomainNominal FrequencyRequired FrequencyMaximum FrequencyViolation
      CyILOCyILO1.000 kHz1.000 kHz N/A
      CyIMOCyIMO8.000 MHz8.000 MHz N/A
      CyMASTER_CLKCyMASTER_CLK80.000 MHz80.000 MHz N/A
      CyBUS_CLKCyMASTER_CLK80.000 MHz80.000 MHz49.980 MHzFrequency
      Clock_1CyMASTER_CLK4.000 MHz4.000 MHz43.435 MHz
      CyPLL_OUTCyPLL_OUT80.000 MHz80.000 MHz N/A
      CyXTALCyXTAL8.000 MHz8.000 MHz N/A