1 Reply Latest reply on Dec 27, 2017 1:36 AM by krishnag_71

    S29GL01GS did I just screw up WE# vs. CS# ?


      Hello, I have a design in which I have S29GL01GS connected 16-bit data bus to a Microsemi Smartfusion FPGA with a processor and the External Memory Controller.  https://www.microsemi.com/document-portal/doc_download/130935-ug0250-smartfusion-microcontroller-subsystem-user-guide I followed the directions, but perhaps not closely enough because I missed the part about connecting one of the byte-enables from the EMC to the WE# pin on the flash; in this manner, what is supposed to happen (set CSFE = 0) that CS# is low all the time, and BYTE_EN# from the memory controller becomes WE# on the flash and it toggles every transaction.


      Well, what I did do is connect RW_N on the memory controller to WE# on the flash.  In write operations, WE# will be a constant low.  The previously mentioned byte enable lines are not used.  Oh well.  However, then I read Section 9.5.1 Asynchronous Write in the S29GL01GS datasheet, where it says:


      When WE# is Low before CE# goes Low and remains Low after CE# goes High, the access is called a CE# controlled Write. A CE#

      controlled Write transitions to the Standby state.

      If WE# is Low before CE# goes Low, the write transfer is started by CE# going Low. If WE# is Low after CE# goes High, the address

      and data are captured by the rising edge of CE#. These cases are referred to as CE# controlled write state transitions.


      There is an operating mode in which CE# toggles with every transaction.  Am I saved here?  Any downsides to counting on this?  The board is currently getting built so I'm currently stuck with what I have.