1. As per Type-C SPEC, the attached event is depends on hardware, which is means vRd (the divide voltage of Rp and Rd on CC line). If CCG3 is power source, CCG3 present Rp on CC line and monitor the voltage of CC. When UFP attached, the CC line will be have a fixed divide voltage, then CCG3 need identify it and enable 5V on VBUS. And then advertise SOURCE_CAP.
2. For CCG3 firmware, the API is listed in config.h. You just need configure which Type MOS FET in Main.c is okay.
/* Function/Macro to turn power source for P1 OFF. */
#define APP_VBUS_SRC_FET_OFF_P1() pd_internal_cfet_off(0, false)
#define APP_VBUS_SRC_FET_OFF_P1() pd_internal_pfet_off(0, false)
#endif /* CCG3_FLIPPED_FET_CTRL */
/* Function/Macro to turn VBUS_DISCHARGE FET for P1 ON. */
#define APP_DISCHARGE_FET_ON_P1() pd_internal_vbus_discharge_on()
How to config MOS FET for CCG3 in main.c
* Configure the FET type usage model. This should be modified only if
* the board supports a different configuration. Wrong configuration
* shall result in damage of the boards and attached devices. Leave it
* to default configuration for working with standard cypress design.
* For CCG3, the default is N_JN_FET for all gate drivers.