1 Reply Latest reply on Dec 27, 2017 11:40 PM by lisz

    Control method of VBUS_P_CTRL

    user_474444345
    user_474444345 Dec 25, 2017 1:25 AM

      Hello,

       

      About CYPD3125-40LQXI,

       

      I work CCG3 as DFP at first and I will activate Rp on CC1 and CC2.

      And when UFP is connected though EMCA, I think that CCG3 have to open VBUS FET by controlling VBUS_P_CTRL0/1 pins.

       

      Q1) How can I know CC1 or CC2 is connected and the voltage is correct for connecting to UFP in CCG FW? any interrupt happen?

       

      Q2) How should I control the VBUS_P_CTRL0/1? any API prepared?

       

      Best regards,

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        • 1. Re: Control method of VBUS_P_CTRL
          lisz
          lisz Dec 27, 2017 11:40 PM (in response to user_474444345)

          Hi Takeshi,

           

          1. As per Type-C SPEC, the attached event is depends on hardware, which is means vRd (the divide voltage of Rp and Rd on CC line). If CCG3 is power source, CCG3 present Rp on CC line and monitor the voltage of CC. When UFP attached, the CC line will be have a fixed divide voltage, then CCG3 need identify it and enable 5V on VBUS. And then advertise SOURCE_CAP.

          2. For CCG3 firmware, the API is listed in config.h. You just need configure which Type MOS FET in Main.c is okay.

          -----------------------

          /* Function/Macro to turn power source for P1 OFF. */

          #if CCG3_FLIPPED_FET_CTRL

          #define APP_VBUS_SRC_FET_OFF_P1()                   pd_internal_cfet_off(0, false)

          #else

          #define APP_VBUS_SRC_FET_OFF_P1()                   pd_internal_pfet_off(0, false)

          #endif /* CCG3_FLIPPED_FET_CTRL */

           

           

          /* Function/Macro to turn VBUS_DISCHARGE FET for P1 ON. */

          #define APP_DISCHARGE_FET_ON_P1()                   pd_internal_vbus_discharge_on()

          -----------------------

          How to config MOS FET for CCG3 in main.c

              /*

               * Configure the FET type usage model. This should be modified only if

               * the board supports a different configuration. Wrong configuration

               * shall result in damage of the boards and attached devices. Leave it

               * to default configuration for working with standard cypress design.

               *

               * For CCG3, the default is N_JN_FET for all gate drivers.

               */

              pd_hal_set_fet_drive(PD_FET_DR_N_JN_FET, PD_FET_DR_N_JN_FET);

           

          Best Regards,

          Lisa