Please share the screen captures of NiosII command shell, to check what you input and NiosII outputs.
Thanks for your reply!
I run these commands in order from top to bottom:
1) jtagconfig -n
2) nios2-configure-sof SPI_Controller.sof
3) nios2-flash-programmer --epcs --base=0x120000 --debug
4) sof2flash --epcs --input=<my design file>.sof --output=<your design file>.flash
5) nios2-flash-programmer --epcs --base=0x120400 <my design file>.flash
The screenshots by (2) and (5) :
By the way, I think the board I'm working with is wired correctly since the FPGA configures correctly when an EPCS16 configuration device is used.
Thanks for the info and screenshots.
Could you try to verify the device contents by adding --verify option to the step (5)?
Looks like your file is programmed correctly.
You mentioned that "Besides, I have also tried to program .jic file by "Disable EPCS ID Check" in Quartus II 13.0 but not working".
Does it mean "program succeed but config failed" or "program failed"?
(1) "Besides, I have also tried to program .jic file by "Disable EPCS ID Check" in Quartus II 13.0 but not working".
which is mean I using Quartus II 13.0 sp1 and I enable the"Disable EPCS ID check" option in Convert Programming File tool, then generate a .jic file for Quartus II programmer to program my flash device. But Not working.
(2)Does it mean "program succeed but config failed" or "program failed"?
Continue (1), it shows " Error: Can't recognize silicon ID for device 1." in processing message window.
by this method(Quartus II programmer), my program can't be executed.
I'm curious about why doesn't the FPGA configure correctly with cypress flash devices, since it seems to program and verify without error.
I have no idea how to debug this problem now(I'm a newbie),
I am reading some articles about flash programmer,
And It may be a dumb questiones......
1) should I add Serial Flash Loader IP core in my project?
I mean when I program cypress flash device completely, then how the FPGA be configured from the cypress flash device?
2) I am not sure the base address of on-chip memory in my Qsys setting is right or not, is it possible that I set the wrong address?
Any recommend I would be appreciated!
1) You don't need to add SFL IP in your project
2) According to NiosII shell's trace you send, it's OK
I checked .jic file with "Disable EPCS ID Check" method by using Cyclone V + FL128S, using Quatus Prime 17.0.
Both programming and configuration succeeded.
Could you try with Quartus Prime 17.0 for programming via jic file?
I will try with QuartusII 13.0 sp1 on my side.
But...It seems that Quartus II 17.0 does not suport the stratix II FPGA device,
the latest supported version for statix II is 13.0sp1, which I found in the download center of Altera website.
And I have already tried with Quartus Prime programmer 17.0 for programming flash device via .jic file(the .jic file with "Disable EPCS ID Check" is generated from Quartus II version 13.0sp1). It's not working.
I will try another Quartus II version,
thank you for your reply!
Could you try to use JTAG to configure the FPGA, instead of using Flash?
This is for checking your .sof file is valid or not, just in case.
There's no doubt that i can configure FPGA with .sof file via JTAG.
I did some tests and found that the data programmed into Flash was not correctly.(This is my result after the following tests)
Since It could be FPGA boot up failure or Flash program failure,
I have to measure the input and out signals of Flash, which are DCLK, ASDI, and DATA.(pin16, pin15, pin8 of S25FL128SAGMFI011)
All signals are look fine......they show up normally at the right moment and take a proper time when Flash is Programing(Erasing).
But all signals are dead when I reboot the FPGA by power on/off.
For checking the data programming Into Flash, after I complete the steps (1) to (5) as I mentioned previously on December 21.
I configure FPGA again with .sof file through JTAG, then send command to Flash.
for example, Read Flash signature 0xAB, I can get 0x17, and this is right.
other commands like program or erase, can also be verified well.
And I think I've found the problem, I read the address of 0x120000 to 0x120400 and found no data in this range.(all 0xFF)
I can find some none 0xFF address in earlier addresses, but it was not very closer to address 0x120400, (not bit shifting caused?)
Now, I am asking a software man to help me to retrieve all the data from Flash, It's diffcult for me to compare these data...
Any idea? (Any progress on this issue, I'll inform you immediately.)
The problem is solved.
Now, FPGA can boot from Cypress Flash successfully.
Because I couldn't find problem on this issue, so I used another board(the same Cyclone series)for testing.
And found that all process can be performed easily and successfully just by Quartus II 10.1 programmer(should check the Disable EPCS ID option when generating a programming file, or FPGA will not boot up from Flash)
Anyway It was obviously my hardware problem. Sorry for wasting your time so much!
Thanks for letting me know that the problem was solved. I'm glad to know that!