6 Replies Latest reply on Dec 13, 2017 1:04 AM by jiwac_1319726

    FLAG  takes too many time to  go back to high


      I am developing FX3(CY3014) +FPGA(altera) to upload counter(do not stop ) data to PC。 FPGA logic consists of counter (1M CLOCK, 32bit BUS) +FIFO +USB interface module。My USB interface and FX3 firmware is  using the application notes AN65974 。I use the streamer mode 's  firmware and logic ( I added counter and FIFO ). PC software is the streamer application in the  SDK.

      Now, I have a  serious problem  to upload counter data. I find that ,after one bulk transfer (16kB ), flagA (indicates the up Endpoint  DMA ready)   takes too many time (about several hundred microsecond )to go back to high . During the time , counter generate so many data that make the FIFO full ,thus the PC can not receive continuous  counter data, some time the software just stuck without writing any more data to file.

      The software just use the streamer application in the SDK, I just modify it  to write to disk after transfer enough data.


      The attachment is the code that I modified to write data to disk file. It is part of "XferLoop" function of streamer application.



      How can I solve this problem?