One or two bus clock cycles in the fomula of FLmin/FLmax are additional bus clock cycles required by MFS circuit to sample the inputs.
The theoretical FLmin and FLmax formula is,
FLmin=(11bits * (V+1) – (V+1)/2 + 1)/φ
FLmax=(21/20 * 11 * (V+1))/φ
However, practically MFS requires one or two additional bus clock cycles to sample the inputs. Thus, practical formula for FLmin and FLmax is;
With the sampling timing margin of one bus clock (φ), FLmin = (11bits × (V+1) - (V+1)/2 + 2)/φ
With the sampling timing margin (φ) of two bus clocks (φ), FLmax=(21/20 * 11 * (V+1) - 44/20)/φ