Minimum requirement for FRAM CS-High to power-down (TPD) timing

[Anonymous]

Hi,

Looking at the datasheet of FM25V20A and CY15B102Q FRAMs, under power cycle timing section, the Tpu parameter "CS-HIGH to power-down (VDD(min))" is 0us minimum. Does this mean that there is no minimum requirement for the chip select line to remain high before VDD drops below the minimum threshold?

I know this has been a problem in the past for FRAMs, but even the following app note talking about it has been obsoleted: http://www.cypress.com/documentation/application-notes-obsolete/f-ram-tm-spi-read-and-write-internal...

AN302 - F-RAM™ SPI Read and Write Internal Operation and Data Protection | Cypress Semiconductor .

Does this mean that the chip select line not holding up during power down is No longer a problem with Cypress' FRAMS?

Many thanks for your help.

Roberto

[PradiptaB_11]

Hi Roberto,

You are referring to the tPD parameter here in this case. For the above parts you have mentioned there will be no such minimum requirements for the chip select line to remain high before VDD drops below the min threshold. The spec is 0 us.

Thanks and Regards,

Pradipta.

[Anonymous]

Hi Pradipta,

Thanks for your answer. Yes, I was referring to tPD. Do you know by any chance what has changed from previous FRAMs and why this is not a problem now?

Regards,

Roberto

[PradiptaB_11]

Hi Roberto,

There has been changes in the design of the FRAMs so that we have overcome this shortcoming in the earlier versions.

Thanks,

Pradipta.