2 Replies Latest reply on Jan 28, 2018 4:51 PM by rduran_2989376

    Minimum requirement for FRAM CS-High to power-down (TPD) timing

    rduran_2989376

      Hi,

       

      Looking at the datasheet of FM25V20A and CY15B102Q FRAMs, under power cycle timing section, the Tpu parameter "CS-HIGH to power-down (VDD(min))" is 0us minimum. Does this mean that there is no minimum requirement for the chip select line to remain high before VDD drops below the minimum threshold?

       

      I know this has been a problem in the past for FRAMs, but even the following app note talking about it has been obsoleted: http://www.cypress.com/documentation/application-notes-obsolete/f-ram-tm-spi-read-and-write-internal-operation-and-data

      AN302 - F-RAM™ SPI Read and Write Internal Operation and Data Protection | Cypress Semiconductor .

       

      Does this mean that the chip select line not holding up during power down is No longer a problem with Cypress' FRAMS?

       

      Many thanks for your help.

       

      Roberto