1 Reply Latest reply on Dec 11, 2017 6:05 AM by AchimE_41

    The access to MCWDT from CM0  and CM4


      I would like to ask about MCWDT.


      On 198 pages of PSoC 63 with BLE Architecture Technical Reference Manual, there is an description that

      a single MCWDT is not intended to be used by multiple CPUs simultaneously.


      [Question1] What may happens if a single MCWDT is used by multiple CPUs simultaneously?

      [Question2] Why is the use of single MCWDT by multiple CPUs simultaneously banned?


      Best Regards


        • 1. Re: The access to MCWDT from CM0  and CM4



          It is not banned directly, but the hardware is not [let's call it] "thread save".


          Two examples where you get problems with two cores:

          1. if you want to prevent the device from getting stuck in the code -> perform reset if not responding. If core0 gets stuck, core1 will still reset the WDT and no reset will be generated.
          2. If you want both cores to trigger on periodic interrupts generated by the same WDT and one core is busy in a higher prioritized ISR and the other core clears the Interrupt flag, WDT ISR will be missed on the busy core.


          The second one might be solvable by a semaphore like construct, where you wait for the second core to enter the ISR as well.