I'm using a cyusb3014 to transfer 32-bit width data between FPGA and PC.
1.The FX3 works as a slave Fifo BULK mode.
2.The interface's clock rate is 100M, generated from FPGA.
3.I had configured four endpoint in FX3.
1) EP0: data transfer from PC to FPGA. FlagA: TH0_DMA_READY(GPIO21).
2) EP1: data transfer form FPGA to PC. FlagB: TH1_DMA_READY(GPIO22).
3) EP2: data transfer form FPGA to PC. FlagC: TH2_DMA_READY(GPIO23).
4) EP3: data transfer form FPGA to PC. FlagD: TH3_DMA_READY(GPIO25).
Problem is :
Read and write operation with low rate(~10kB/s) on each endpoint is successed. But, When read data from EP3 with high speed (~250MB/s), the transmission will be interrupted random.
1)the interruption period looks random（mins to hours).
2)The length of the read out data by method XferData () is 0 on PC,
3)and the flagD (hight, not ready) disable FPGA write data to FX3.
4)the transmission on other endpoint is correct.
5)I can reset the endpoint by "USB control center", and the transition is correct again.
Sometime, the FX3 will be removed from Win7 system and plugged again with the firmware is ok(program in RAM).
What kind of fault is this? how to locate the cause of the failure, and what suggestions for improvement?