5 Replies Latest reply on Dec 9, 2017 6:25 AM by mahec_674091

    Trying to Implement a 32 MHz Manchester Encoder/Decoder


      Hello All,
      I am very impressed with the PSOC 6 and am enjoying working with the BLE development kit.


      I am working on a project that needs the ability to both encode and decode 16 bit data in a Manchester format, running at a clock rate of 32 MHz.  I have looked at the code for the Manchester Encoder/Decoder for PSOC 3 and it is very straightforward.  However, it uses an SPI element that has an upper frequency limit of 25 MHz.  So, I suspect that I need to create the Manchester Encoder/Decoder using the UDB blocks.


      As a start . . . when receiving data at 32 MHz, I need to Manchester decode the serial stream and write the data to RAM at a 2 MHz rate.


      I have never worked with Cypress UDB blocks.  I suspect the best way to implement this functionality would be to make a custom UDB block based upon Verilog code.  Before embarking on this . . . anyone have an idea whether this would even be feasible with PSOC 6?


      Thank you for your help,