I cannot see an interrupt handler in your code snippet nor a ist_SPI_RX_StartEx(InterruptHandler).
I would recommend to set the SPI Byte mode and increase the buffers to 16.
When still got stuck, can you please post your complete project so that we all can have a look at all of your settings. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
I attached the project file.
I prepared both "SPIMH_INTR_RX_NOT_EMPTY" and "SPIMH_INTR_RX_FIFO_LEVEL" interrupt instead of "SPIMH_INTR_RX_FULL".
The project are not necessarily "SPIMH_INTR_RX_FULL".
"SPIMH_INTR_RX_NOT_EMPTY" and "SPIMH_INTR_RX_FIFO_LEVEL" are same behavior because SPIMH_SetRxFifoLevel is set to 1.
"SPIMH_INTR_RX_NOT_EMPTY" runs well but "SPIMH_INTR_RX_FIFO_LEVEL" does not run well.
If you set "#define rx_not_empty" in FRAM_SPI.h, "SPIMH_INTR_RX_NOT_EMPTY" interrupt is set. On the other hand, if you comment out it "SPIMH_INTR_RX_FIFO_LEVEL" interrupt is set.
the codes is changed in FRAM_SPI.c below. and I think that SPIMH_SetRxInterrupt and SPIMH_SetRxInterruptMode are allowed interrupt.
temp = SPIMH_GetRxInterruptSource();
temp = SPIMH_SpiUartGetRxBufferSize();
I am using CY8CKIT-044 and CY15FRAMKIT-001.
I had a mistake in CY_ISR(isr_SPI_RX_CustomInterrupt).
and I am trying "SPIMH_INTR_RX_FIFO_LEVEL" interrupt.
Please correct it below.
I can finally run well with the RX FIFO Level.
I would like to confirm two settinigs.
Are they right?
1. Should I set the RX FIFO Level to 0 If I want to generate an interrupt when receiving 1 byte
(RX data bits = 8 in the configuration of SPI) data?
2. May I set SPIMH_SetRxInterruptMode() function to enable and disable the RX FIFO Level interrupt?
[when enabling the RX FIFO Level interrupt]
[when disabling the RX FIFO Level interrupt]
I measured both "in case of enabling RX FIFO level interrupt with SPI master configuration" and "in case of enabling RX FIFO level interrupt after writing the memory address with API" the execution time. It was improved from 171.68us to 111.77us.
in case of enabling RX FIFO level interrupt with SPI master configuration
in case of enabling RX FIFO level interrupt after address write with API