8 Replies Latest reply on Jan 4, 2018 6:08 AM by marc_1615421

    How can I debug the MIPI CSI-2 RX interface?

    marc_1615421

      Hi

       

      I'm using the Denebola RDK together with a custom camera board. I started from the UVC firmware example and configured the MIPI RX according to my needs. I also enabled debugging mode and the MIPI error thread. The camera board I'm using is a custom design with my own FPGA implementation of a MIPI CSI-2 TX. It is likely that I have a few bugs there but I have no way of testing it (apart from simulation) because I don't have a high-end oscilloscope. I tought that I could use the CX3 for debugging. I was expecting that I could hook it up and that I would observe some MIPI errors from the MIPI error thread. However, I don't receive any errors. I'm explicitly printing the error count every 5 seconds and it always returns 0. I'm also printing the state of the GPIF state machine and it seems to be locked in state = 2. What could be possible problems and why don't I receive any MIPI error messages?

       

      Thanks,

       

      Marc

        • 1. Re: How can I debug the MIPI CSI-2 RX interface?
          ludovic.tramart_1679866

          With a basic oscillosope you can start watching these testpoint on the CX3: PCLK_TESTPOINT, HSYNC_TESTPOINT, VSYNC_TESTPOINT.

           

          If your mipi is correctly configured, it should be able to recreate these clocks signals. If not then you have an issue with your mipi configuration.

           

          Unfortunately, I don't remember if those signals are available on the Denebola  board... :-(

           

          Best regards,

          Ludovic.

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          • 2. Re: How can I debug the MIPI CSI-2 RX interface?
            marc_1615421

            Thanks for your reply. Unfortunately, it looks like these signals are not available as classical test points on the Denebola board. Maybe they exist as BGA vias - I'm going to look into that.

             

            Meanwhile, what should I expect from these signals? PCLK sounds like the pixel clock of the parallel output interface from the MIPI RX. I guess this clock is only generated when it actually succesfully reads form the MIPI interface. So you are saying that if this clock is not generated, it doesn't receive anything at the MIPI interface...

            • 3. Re: How can I debug the MIPI CSI-2 RX interface?
              ludovic.tramart_1679866

              Yes, it doesn't received anything, or mipi settings are wrong on CX3. In bothcase you won't get coherent video clocks (i.e. pixel clock, hsync, vsync).

              • 4. Re: How can I debug the MIPI CSI-2 RX interface?
                ludovic.tramart_1679866

                I also found out that starting to transmit on mipi line while the CX3 mipi block is not yet wake up is not a good idea.

                 

                So your CX3 code needs to be able to activate/deactivate mipi transmission on your fpga.

                 

                Hope it helps

                 

                Ludovic.

                • 5. Re: How can I debug the MIPI CSI-2 RX interface?
                  marc_1615421

                  I was expecting that and therefore I implemented activation and deactivation of MIPI transmission through the MIPI sensor shutdown signal.

                   

                  I've already got a reply from e-con systems. Indeed, the test points are available through  BGA vias:

                   

                  1. PCLK     - TP 16

                  2. HSYNC  - TP18

                  3. VSYNC  - TP20

                   

                  The test points are only marked in the assembly drawing:

                   

                  denebola_tp.PNG

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                  • 6. Re: How can I debug the MIPI CSI-2 RX interface?
                    savj

                    Hi,

                     

                    GPIF state = 2 means that GPIF is waiting for the frame valid signal and line valid signals to go high. In MIPI terms, once CX3 MIPI Block receives FRAME SYNC and LINE SYNC packet it will assert Frame valid and line valid signals (Logic 1).

                     

                    Please ensure that CX3 MIPI block is out of reset, configured and ready to receive video data. i would suggest you to use the standard CX3 example code generated from Eclipse USB suite through CX3 configuration utility (Just to be sure that CX3 settings are correct) . Once the CX3 MIPI parameters are correctly configured, you should definitely see the Frame valid signal and/or line valid change from logic 0 to 1. I think MIPI Transmitter will not be sending proper data if HSYNC and VSYNC are not asserted.

                     

                    Regards,

                    Savan

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                    • 7. Re: How can I debug the MIPI CSI-2 RX interface?
                      yyca

                      Hi,

                       

                      Just like Savan said, please check if the TX part asserts FV/LV correctly.

                      • 8. Re: How can I debug the MIPI CSI-2 RX interface?
                        marc_1615421

                        Actually, I'm using the example code generated fromEclipse USB Suite. To me, it seems that FV and LV are not asserted correctly so probably it doesn't receive the synchronization packets properly. But I was hoping that there is a way of finding out where it fails. I was expecting that the MIPI error thread could give further insights on what happens on the MIPI RX side. But I don't receive any errors there so I assume it even fails receiving the start of transmission synchronization pattern...