I'm using a CYUSB3KIT to transfer 32-bit width data from another data source device. The FX3 works as a slave, and the external data source device is the master. The interface's clock rate is 75M, generated from master. The interface is one-direction, data transfer from external to FX3 only. There is no write enable signal, so the validity of data is controlled by disabling the clock at master. Two flags are used. One is TH0 ready, one is TH0 WM. State machine only have one DMA channel, always use TH0 to send and wait if TH0_READY is not active.
Problem is :
The master stops sending clock edges when READY or WM is not active, but the two signals will not be active forever. if I force the master to send clocks, after sending about 32 clocks, the two signals are valid.
And for more, I found that the polarity of these two signals are reversed to the setting in GPIF. The signal is set to be active high, but measured to be active low (by forcing the master to send clocks without receive from host, the two signals should be not ready).
Anyone can help me?
Sorry I found that I post it in wrong place, I will post it in the correct place.
Admin, please delete this.