Theoretically speaking you should see a very small decrease in Isb when Vcc is decreased. The internal memory architecture is the deciding factor for how much % decrease/increase you observe.
Hi Pradipta san,
Thank you for your reply !
It is good information.
I think SRAM has internal LDO for each memory cell.
So even if Vcc decreased, voltage level of cell keep stable.
Is it correct ?
Yes, the memories now a days have internal LDO to regulate the VCC and GND. So that is why the internal design becomes important. Say if i decrease the Vcc it may happen the Quiescent current of the memory cell/LDO decrease, similarly you can see a small dip in the Isb current. Or you can say that there can be provisions in the design to provide some extra current when Vcc drops to maintain the device performance. So in this case you might actually see a increase in current sometimes.