One of the possible reasons could be power loss during write register operation when you boot up.
Please refer to the KB article from the link given below which explains about the recovery if incorrect write register operation has been performed.
thank you for the answer.
We are not issuing WRR in our code, but I found "XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */" in the Xilinx qspi driver used by the first-stage bootloader. So perhapse the QUAD bit is indeed set during boot, as mentioned in the KBA.
Power-cycling during boot is something that could have happened to the system.
So w.r.t. my acute problem:
As far as I understand I won't be able to reset the OTP Bit for BPNV to zero. Hence BP0-2 will default to 1, leaving the flash locked after power on.
But if I could reset SRWD to zero (don't know about the WP# state), there could at least be the chance to reset the volatile bits?