To your questions:
1. All the peripherals are accessible to both CM4 and CM0+, as both share the same MMIO and Memory address space. That said, you cannot access any of these peripherals in DeepSleep and Hibernate modes from the CPU, as your CPU will be powered-off in these modes These peripherals can generate interrupt and wakeup the CPU (either M4 or M0+ or both) in DeepSleep and the system in hibernate (as wakeup from hibernate mode is a system reset event not CPU wakeup).
2. No. Both the cores can see the entire register space. That said both CM0+ and CM4 have their own ARM defined system space registers (includes interrupt priority, enable/disable etc. registers). These registers are visible only to the core that access it.
3. No. It should not matter between 62 and 63 devices.
Let me know if this helps.
Meenakshi Sundaram R
Hello Meenakshi Sundaram R-san,
Thank you for answering.
May I ask you an additional question?
You said "you cannot access any of these peripherals in DeepSleep and Hibernate modes from the CPU"
Does this mean that the API that is output to the peripheral during Deepsleep and Hibernate modes is invalid?
What I meant is you cannot execute code (that access the peripheral) when you are in DeepSleep or Hibernate mode as your CPU is OFF
The peripheral is capable of operating in DeepSleep/Hibernate modes, if they are configured and support to run in those modes.
So, peripheral operation in DeepSleep/Hibernate modes - Yes.
CPU operation (hence access) in Sleep/DeepSleep/hibernate modes - No.