0 Replies Latest reply on Dec 3, 2017 10:37 AM by h.ahuis_2374911

    Slave FIFO FPGA Design: Role of DDR

    h.ahuis_2374911

      Dear all,

      in the Slave FiFo Example of FX3 I would like to implement the design on an Altera Cyclone V Device. In the example design provided by Cypress I wonder what's the reason to route the 100 MHz Clock, I assume it is the PCLK from FPGA to FX3, through a DDR instantiation:

       

       

      --pll instantiation

      pll_inst_clk : pll

      port map(

           areset => '0',

           c0         => clk_100,

           inclk0     => clk,

           locked => lock

              );

       

       

      ---ddr instantiation

      ddr_inst_to_send_out_clk_to_fx3 : ddr

            port map(

                   datain_h   => '0',

                   datain_l   => '1',

                   outclock   => clk_100,     ------------> This is the 100 MHz Clock coming from above instantiation of PLL.

                   dataout => clk_out          ------------> This one goes out of FPGA into FX3 (PCLK)

           ); 

       

       

      --fifo instantiation for LoopBack mode

      fifo_inst : fifo

      port map (

         din        => fifo_data_in,

                         write_busy   => fifo_push,

                         fifo_full    => fifo_full,

                         dout         => data_out_loopback,

                         read_busy    => fifo_pop,

                         fifo_empty   => fifo_empty,

                         fifo_clk     => clk_100,

                         reset_al => reset_n,

                         fifo_flush   => fifo_flush

      );

       

       

      Driving this stuff and looking with Altera Signal Tap II at signal dataout it always stays '0', but outclock has falling and rising edges with correct timing for 100 MHz.

      Am I seeing something wrong here?

      Kind regards.