I am working with FX3S USB 3.0 controller.
In design FPGA is the master FX3S is slave.
I am using FPGAmaster Verilog code is provided by cypress and I created a block in Vivado .
providing 27MHz input clock to FPGAmaster block and output also 27MHZ clock from FPGAmaster block.
Here, my question will be.
What is expected latency from FPGAmaster block?
Please suggest me regarding this.
Thanks and Best Regards