ModeBit Reset(FFh) S25FL-S

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Anonymous
Not applicable

Hello,

Suppose that we execute ModeBit Reset(FFh) as the first instruction after power on.

Is there any trouble to all the target devices below? Or this instruction will be ignored?

S25FL128S

S25FL256S

S25FL512S

S70FL01GS

Note: In the above device, DDR is not used, only Standard SPI / Quad SPI is used.

I've referenced the S25FL-S datasheet, there are a description below.

>It is recommended to use the MBR command after a system reset when the

>RESET# signal is not available or, before sending a software reset, to ensure the device is released from continuous high performance read mode

I understand that there should be no issue if we execute FFh after POR, is it correct?

Please tell if there are any attention about execute MBR command.

Best Regards,

すべての対象デバイスでは、デバイスに不都合な事が発生しますでしょうか?

それとも、このインストラクションが無視されるだけでしょうか?

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1 Solution
Anonymous
Not applicable

Hello Nam Son Tran,

Q) Is there any trouble to all the target devices below? Or this instruction will be ignored?

A) No there is no problem.

Q) I understand that there should be no issue if we execute FFh after POR, is it correct?

A) Yes you are correct.there shouldbe no issue.

Thanks,

Krishna.

View solution in original post

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6 Replies
Anonymous
Not applicable

Hello Nam Son Tran,

Q) Is there any trouble to all the target devices below? Or this instruction will be ignored?

A) No there is no problem.

Q) I understand that there should be no issue if we execute FFh after POR, is it correct?

A) Yes you are correct.there shouldbe no issue.

Thanks,

Krishna.

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Anonymous
Not applicable

Hi Krishna,

Thanks for your answer, I have has another question regarding the target device below.

S25FL128S

S25FL256S

S25FL512S

S70FL01GS

Note: DDR is not used, only Standard SPI / Quad SPI is used.

■Question: Which Psck is being used when calculating the minimum value of tWH(tCH) or tWL(tCL) ?

1) Frequency that device is using?

2) Fsck,c (max) 133MHz ?

3) The highest frequency after setting the dummy clock with LC bit?

   Eg. In SDR High Performance mode, LC = 00 (EBh/ECh Mode=2, dummy = 4). Psck max = 80MHz

4) Others?

Best Regards,

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Anonymous
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Hello Nam son tran,

Q) Which Psck is being used when calculating the minimum value of tWH(tCH) or tWL(tCL) ?

A)  The minimum value is 45% of Psck. So the value depends on the frequency you are operating.

Q) The highest frequency after setting the dummy clock with LC bit?

A)  In SDR high performance mode it is 133MHz, LC = 00 and Dummy cycles = 8

Thanks,

Krishna.

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Anonymous
Not applicable

Hi Krishna,

I know the minimum value is 45% of Psck. What I'm asking is : which Psck is used to calculated?

1) 2) 3) or 4)?

Notice that DDR is not used, only Standard SPI / Quad SPI is used.

Regards,

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Anonymous
Not applicable

Hi Krishna,

Could you update your response on my latest question??

Regards,

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Anonymous
Not applicable

Hi Nam son Tran,

The frequency that is used for calculating Psck is the one which the device is operating at that point. i.e option No 1).

Thanks,

Krishna.

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