The PKTEND signal needs to be toggled only when any DMA buffer is not completely filled. For example, assume that you have 6 DMA Buffers each of size 16K. After first 5 DMA Buffers are filled they will be wrapped (ready to be sent to the USB) and then can be committed (transferred to the USB Peripheral). Assume that the 6th DMA Buffer is partially filled and the FPGA has no more date to be sent. Now the PKTEND signal is asserted (pulled low), so the Buffer is wrapped.
Can you please let us know how much data is the PC able to receive, how much data is being lost and how much data is actually sent be the FPGA, details of your buffer count and size, Debug logs if any?
- Madhu Sudhan
Thank you for your reply. Actually, I wanted to understand why this sample program did not work, thereby I tried to test the different sections of it. As a matter of fact, When PKTEND was toggled, while the rest of the program remained unchanged, data was transferred without any lost.
Finally, last week I could have a data transferring via the same platform (Virtex-5 + EZ-USB FX3) by another program. Personally, I think AN65974 program may have some problems specially in the sections related to FlagA/B.