In AN84868, the SPI pins used for FPGA configuration occupy some of pins in D16~D31. I've observed when configuration, "io_cfg.isDQ32Bit = CyFalse;". After the configuration, "io_cfg.isDQ32Bit = CyTrue;" to allow 32 bits slave FIFO operations. Does this mean the SPI GPIO should be routed to both the FPGA configuration pins and general IO pins? The branches is inevitable if this is the cases. Will the branches cause the signal integration problem and if so, how to avoid it?
The AN84868 is a series configuration example? how can I use parallel configuration? Can I use CyU3PGpioSimpleSetValue to control the GPIOs connected to CCLK and 8 data pins of the FPGA? CCLK will be good enough to tranfer data? 8 data pins can update value at the same time? will the function CyU3PGpioSimpleSetValue run with an uncertain speed that causes the timing problems?
As to my understanding, In the configuration example AN84868, the configuration data are entirely stored at the FX3 before the vender command is sent. Some FPGA have a small volumn of configruation data and therefore can be stored. The configruation data of the FPGA I use achieves 2.7M Bytes. Is the ram of FX3 large enough to hold the data? If not, is there any solution?