1 Reply Latest reply on Nov 29, 2017 12:25 PM by psai

    Which IRQs flags are cleared automatically?

    user_246598725

      Hi,

       

      I remember there's a Cypress document which contains a table listing the IRQs which clear their pending flag automatically on ISR entry on a PSoC 4/5 (Cortex M0/M3). Unfortunately I forgot which document contains this table

      Anyone knows this document?

       

      Regards

        • 1. Re: Which IRQs flags are cleared automatically?
          psai

          Hi,

           

          There does not seem to be a ready document for this. The documents related to this topic would be the below, but could not find a direct table answering the query in these:

           

          The PSoC5LP Architecture TRM(Interrupt Controller chapter): http://www.cypress.com/file/123561/download

          AN54460 - PSoC 3 and PSoC 5LP Interrupts: http://www.cypress.com/file/44256/download

          AN90799 - PSoC 4 Interrupts: http://www.cypress.com/file/127121/download

          PSoC Creator Interrupt component(isr) datasheet: http://www.cypress.com/file/130976/download

           

          As for the ARM Core in PSoC, for all interrupts, the interrupt component's status gets cleared automatically when the isr runs, as said in page 76 of the above PSoC5LP TRM:

          "Interrupt Entry (IRA) – The CPU acknowledges the interrupt entry. The next assertion in the same interrupt line can be detected only after the interrupt entry. Any assertions before that are ignored. The interrupt controller clears the pending bit upon receiving the acknowledgement."

           

          But the interrupts in the ARM core are triggered by the interrupt statuses or signal edges of the PSoC components. So, you are probably interested in knowing what PSoC components need clearing of the interrupt source, to prevent the interrupts from executing infinitely.

          As said in cy_isr component datasheet, under "ISR_ClearPending()" API description:

          "Some interrupt sources are clear-on-read and require the block interrupt/status register to be read/cleared with the appropriate block API (GPIO, UART, and so on). Otherwise the ISR will continue to remain in pending state even though the interrupt itself is cleared using this API."

           

          What may help is an understanding of the derived/rising edge/level interrupts signals in section "3.1 Interrupt Component Configuration" in the AN54460.

           

          And then you may also check the component datasheets (of the components whose "interrupt" signals you are hooking to an isr component in the project schematic) for APIs to clear the interrupt or status such as "PWM_ReadStatusRegister", or "Pin_ClearInterrupt".

           

          Thanks & Regards,

          Prem Sai