3 Replies Latest reply on Nov 14, 2017 7:36 AM by MeenakshiR_71

    TCPWM in PSoC6 Vs PWM in PSoC 5LP

      Dear all,
      What can be the possible reason for two different results from TCPWM in PSoC6 and PWM in PSoC 5LP? The desired output from PWM running on PSoC5 is correct but using the same configuration for TCPWM on PSoC6 gives the incorrect output.



      PWM in PSoC5LP

      TCPWM in PSoC6

        • 1. Re: TCPWM in PSoC6 Vs PWM in PSoC 5LP

          Hello muyac_1490236,


          Can you share the settings for the pwm1 and pwm2 component in PSoC 6?


          From what I see it appears like the start is not getting registered on every second cycle. From a functionality stand-point, it seems sort of expected (will confirm once you share the settings). I believe you have configured pwm2 as oneshot and triggering it on rising edge on the line_n output. Now in order for the start signal to be processed or take effect, the counter should not be running and should be in stop state. Again, I believe your period for both the PWMs is same (??). In that case, when the second start comes the pwm2 might just be stopping and misses the start as it was already running. You can probably verify this by reducing the period of pwm2 by '1'.


          Now, I am not sure why you need to trigger the PWM every cycle?? You can trigger once and let it run. Since both run off the same clock, you should not see any drifts. Any specific use case for this approach?

          • 2. Re: TCPWM in PSoC6 Vs PWM in PSoC 5LP

            Reducing pwm2 by '1' works and many thanks for your reply. Furthermore, the settings are below:

            TCPWM in PSoC6

            PWM in PSoC5LP


            In fact, it's a small part of my project OR you can say that I am trying to translate a project on page 20 of "AN76439 - PSoC® 3 and PSoC 5LP - Phase-Shift Full-Bridge Modulation and Control" for PSoC 6.

            • 3. Re: TCPWM in PSoC6 Vs PWM in PSoC 5LP



              As I mentioned, the behavior is expected. Since the period of both the PWMs are same. By the time every other start is triggered, the PWM counter is still running (on the last count) and it ignores the trigger (as start is registered/used only when counter is stopped). By reducing the period by '1' makes sure the PWM stops and accepts the next start trigger.


              Good luck for your design and we will be glad to assist, if you stumble upon any hurdles

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