2 Replies Latest reply on Nov 6, 2017 11:57 AM by user_78878863

    What is the Minimum sampling time of ADC and Maximum Slew rate of DAC

    user_437519798

      I want to know that what is the minimum sampling time using EOS option for SAR or Delta Sigma ADC for sampling rate of more than 250K, i am unable to find this info in the datasheet. Moreover, how much is the tolerance window for end of sampling time i.e. how much time variation every time end of smapling signal is generaed. i want to sample at exact time intervals. so i want to know the time difference/variations for same interval sampling.

      Kindly also tell me what is the maximum slew rate of DAC in PSoc 5LP, how much is rise and fall time of DAC voltage appeared at output, i want to generate a square waveform at DAC output with minimum rise and fall time and higher output rate.

        • 1. Re: What is the Minimum sampling time of ADC and Maximum Slew rate of DAC
          user_78878863

          For the IDAC: the CY8C58LP family data sheet says: settling time to 0.5LSB, range=255µA, full scale transition, fast mode, 600 ohm / 15 pF load : 125ns (table 11-35, page 103 in my version).

          For the VDAC it depends on the scale, for a step from 25% to 75% at 4V full scale its about 3µs (table 11-37, page 106)

          • 2. Re: What is the Minimum sampling time of ADC and Maximum Slew rate of DAC
            user_78878863

            Regarding the SAR ADC: the architecure TRM says:

            The input sampling time can be programmed from the 1 to

            64 cycles in register SARx_CSR2[5:0] register bits. The

            user can also retain the earlier DAC value or clear it at the

            beginning of the new sampling clock. This is done in

            SARx_CSR0[3] register bit. The conversion time is 18

            cycles for input sampling time up to four cycles. The maxi-

            mum conversion time is 78 cycles for input sampling time of

            64 cycles. The sampling time is chosen based on the

            source's input impedance so that the input settling time is

            lower than the sampling time.

            (part 38.2.3)

            and in part 38.2.6:

            The conversion time of the SAR is more than 18 cycles for

            input sampling time of four cycles when hardware trigger is

            used. This is because SOF and EOF are routed through DSI

            routing and these signals encounter a delay, resulting in lon-

            ger conversion time.

            The timing in itself should be consistent, which means its always at the same point in time in reference to the conversion start or end signals (and the clock jitter is, according to the TRM, below 12ps).