For the IDAC: the CY8C58LP family data sheet says: settling time to 0.5LSB, range=255µA, full scale transition, fast mode, 600 ohm / 15 pF load : 125ns (table 11-35, page 103 in my version).
For the VDAC it depends on the scale, for a step from 25% to 75% at 4V full scale its about 3µs (table 11-37, page 106)
Regarding the SAR ADC: the architecure TRM says:
The input sampling time can be programmed from the 1 to
64 cycles in register SARx_CSR2[5:0] register bits. The
user can also retain the earlier DAC value or clear it at the
beginning of the new sampling clock. This is done in
SARx_CSR0 register bit. The conversion time is 18
cycles for input sampling time up to four cycles. The maxi-
mum conversion time is 78 cycles for input sampling time of
64 cycles. The sampling time is chosen based on the
source's input impedance so that the input settling time is
lower than the sampling time.
and in part 38.2.6:
The conversion time of the SAR is more than 18 cycles for
input sampling time of four cycles when hardware trigger is
used. This is because SOF and EOF are routed through DSI
routing and these signals encounter a delay, resulting in lon-
ger conversion time.
The timing in itself should be consistent, which means its always at the same point in time in reference to the conversion start or end signals (and the clock jitter is, according to the TRM, below 12ps).