0 Replies Latest reply on Nov 5, 2017 8:59 PM by shlee_2260611

    AN65974 stream transfer problems

    shlee_2260611

      I've been trying to use AN65974, Designing with the Cypress Ez-USB FX3 DVK and Xilinx FPGA ZC702 Evaluation Board.  I've modified the verilog code for FPGA and firmware for FX3 , but I have trouble with stream IN & OUT transfer. The problems are as follows.

       

      1. CYU3P_PIB_ERR_THR3_RD_UNDERRUN error message when I tried stream out transfer on USB control center.

      - I was attached my firmware code included my GPIF II code.

      - I used GPIF 32bit bus and MANUAL DMA channel for stream IN/OUT transfers.

      - I was transfer out 16384 byte from USB to FPGA through FX3 on USB Control Center. (#define CY_FX_SLFIFO_DMA_BUF_COUNT_U_2_P == 1)stream_out_img.jpg

      - I was found CYU3P_PIB_ERR_THR3_RD_UNDERRUN on UART terminal.

      - I think that my data was transfer to FPGA because I identified SLRD# = Low and SLOE# = LOW at Oscilloscope.

      - So, I can't understand CYU3P_PIB_ERR_THR3_RD_UNDERRUN Error message.
      - Why does that error message occur ? Is there any transfer problem except the error message ?

       

      2. output previous data from DMA buffer when I tried stream in transfer on USB control center.

      - Now my FPGA operate that register of FPGA is written by the data through transfer out and the data read from the register is send to USB through transfer in.

      - I was transfer in 16384 byte from FPGA to USB through FX3 on USB Control Center. (#define CY_FX_SLFIFO_DMA_BUF_COUNT_P_2_U == 1)

      stream_in_img.jpg

      - But I can read the previous data at DMA buffer, not the current data,  through transfer IN.

      - If I would like to read the current data, I must read one more through transfer in.

      - For example

           1. I was TRANSFER OUT "A" data(16384 byte) to FPGA.

           2. I was TRANSFER IN the data from FPGA. But The data read from FPGA was default data of FPGA.

           3. I was 1 more TRANSFER IN the data from FPGA. The data I read was "A" data.

           4. The next I was TRANSFER OUT "B" data(16384 byte) to FPGA.

           5. I was TRANSFER IN the data from FPGA. The data I read was "A" data.

           6. I was 1 more TRANSFER IN the data from FPGA. The data I read was "B" data.

      - I think the cause of problem is due to DMA buffer or GPIF state. ( I can't identify that GPIF state machine enter WRITE STATE through TRANSFER IN. )

       

      - How can I read the current data at once ?