The Endpoint halt problem may due to the host controller or the board you are using. In order to confirm this, please try in a different host controller (PC). Also try using a FX3 DVK to see if the issue is related to your board.
If it is because of the board, please make sure your schematics and layout match with our guidelines in AN70707 application note. For further investigation, please try the following:
1)Can you please print the number of PHY and link errors using the API CyU3PUsbGetErrorCounts(). Please print this continuously. Please check if the value is changing while streaming. If it displays many errors, it means there is a problem with the layout resulting in noise
2) please probe VIO1 and CVDDQ using active probes (during streaming).
Check the peak to peak value of noise(on both cvddq and vio1) while streaming and idle.