4 Replies Latest reply on Oct 21, 2017 7:49 AM by user_438021184

    UART on GPIO48/49?

    user_438021184

      I'm using a SuperSpeed Explorer Kit on a HSMC FPGA mezzanine board.

      I've dowloaded the UART example(1), and it's working. Anything I enter on /dev/ttyACM0 will be observed on the kit's other UART.

      However, I would like to make the UART to use the mezzanine pins on the FPGA. I've changed the source code to this:

       

        CyU3PMemSet((uint8_t *)&io_cfg,0,sizeof(io_cfg));

          io_cfg.isDQ32Bit = CyFalse;

          io_cfg.s0Mode    = CY_U3P_SPORT_INACTIVE;

          io_cfg.s1Mode    = CY_U3P_SPORT_INACTIVE;

          io_cfg.useUart   = CyTrue;

          io_cfg.useI2C    = CyFalse;

          io_cfg.useI2S    = CyFalse;

          io_cfg.useSpi    = CyTrue;

          io_cfg.lppMode   = CY_U3P_IO_MATRIX_LPP_DEFAULT;

          io_cfg.gpioSimpleEn[0]  = 0;

          io_cfg.gpioSimpleEn[1]  = 0;

          io_cfg.gpioComplexEn[0] = 0;

          io_cfg.gpioComplexEn[1] = 0;

          status = CyU3PDeviceConfigureIOMatrix (&io_cfg);

       

      To my understanding this should cause the UART TX to be moved to GPIO48/DQ30, and RX to GPIO49/DQ31. However, I can't seem to get it to work. I don't observe any change on the GPIO_49/DQ31 pin when I transmit data on /dev/ttyACM0. I've also looped rx to tx in the FPGA and would expect to get back whatever I transmitted.

       

       

      Is the above settings correct to use GPIO 48/49?

       

      1)

      http://www.cypress.com/documentation/code-examples/ez-usb-fx3-usb-uart-bridge-example

        • 1. Re: UART on GPIO48/49?
          ntan

          Please refer the "Table 7. CYUSB3012 and CYUSB3014 Pin List" in the FX3's datasheet.

           

          CYUSB301X, CYUSB201X: EZ-USB® FX3: SuperSpeed USB Controller | Cypress Semiconductor

           

          In this table, it is described that the UART-TX and -RX can be assigned to the GPIO[48:49] in a case.

          GS003329.png

          GS003330.png

          But there is a condition that the FX3 is configured as using 16-bit bus GPIF, UART, SPI and I2S.  When this condition is met, the UART-TX and -RX are assigned to GPIO[48:49]  Set useI2S as cyTrue.

           

          In addition, set lppMode as CY_U3P_IO_MATRIX_LPP_DEFAULT to enable all Low Performance Peripheral (LPP) interfaces.  Please refer the section "5.11.2.2 typedef enum CyU3PIoMatrixLppMode_t CyU3PIoMatrixLppMode_t" in the "EZ-USB® FX3 SDK Firmware API Guide" document installed with the FX3 SDK for more details.

           

          Regards,

          Noriaki

          • 2. Re: UART on GPIO48/49?
            user_438021184

            In my latest test I was using the following:

             

              /* Configure the IO matrix */

                CyU3PMemSet((uint8_t *)&io_cfg,0,sizeof(io_cfg));

                io_cfg.isDQ32Bit = CyFalse;

                io_cfg.s0Mode    = CY_U3P_SPORT_INACTIVE;

                io_cfg.s1Mode    = CY_U3P_SPORT_INACTIVE;

                io_cfg.useUart   = CyTrue;

                io_cfg.useI2C    = CyFalse;

                io_cfg.useI2S    = CyTrue;

                io_cfg.useSpi    = CyTrue;

                io_cfg.lppMode   = CY_U3P_IO_MATRIX_LPP_DEFAULT;

                io_cfg.gpioSimpleEn[0]  = 0;

                io_cfg.gpioSimpleEn[1]  = 0;

                io_cfg.gpioComplexEn[0] = 0;

                io_cfg.gpioComplexEn[1] = 0;

                status = CyU3PDeviceConfigureIOMatrix (&io_cfg);

             

            I assume that o_cfg.isDQ32Bit = CyFalse means 16-bit GPIF. But I still don't get GPIO48 to toggle when I transmit. Going back to the other UART works fine.

            • 3. Re: UART on GPIO48/49?
              ntan

              The example project "USBFlashProg" has similar condition using both SPI and UART.

              Following is the IO Matrix configuration from the example project.

               

                  /* Configure the IO matrix for the device. On the FX3 DVK board, the COM port 
                   * is connected to the IO(53:56). So since we need to use SPI, we will have to
                   * either not use UART or use an external UART controller on the IO(46:49). */
                  CyU3PMemSet ((uint8_t *)&io_cfg, 0, sizeof(io_cfg));
                  io_cfg.isDQ32Bit = CyFalse;
                  io_cfg.s0Mode = CY_U3P_SPORT_INACTIVE;
                  io_cfg.s1Mode = CY_U3P_SPORT_INACTIVE;
                  io_cfg.useUart   = CyTrue;
                  io_cfg.useI2C    = CyTrue;
                  io_cfg.useI2S    = CyFalse;
                  io_cfg.useSpi    = CyTrue;
                  io_cfg.lppMode   = CY_U3P_IO_MATRIX_LPP_DEFAULT;
                  /* No GPIOs are enabled. */
                  io_cfg.gpioSimpleEn[0]  = 0;
                  io_cfg.gpioSimpleEn[1]  = 0;
                  io_cfg.gpioComplexEn[0] = 0;
                  io_cfg.gpioComplexEn[1] = 0;
                  status = CyU3PDeviceConfigureIOMatrix (&io_cfg);
              

               

              The difference from your code is I2C is enabled instead of I2S.

               

              I have an another request.  Please look at the UART configuration part to ensure the "flowCtrl" is disabled.  If the "flowCtrl" is enabled, CTS must be controlled or the UART-TX waveform is not observed.

               

                  CyU3PMemSet ((uint8_t *)&uartConfig, 0, sizeof (uartConfig));
                  uartConfig.baudRate = CY_U3P_UART_BAUDRATE_115200;
                  uartConfig.stopBit  = CY_U3P_UART_ONE_STOP_BIT;
                  uartConfig.parity   = CY_U3P_UART_NO_PARITY;
                  uartConfig.txEnable = CyTrue;
                  uartConfig.rxEnable = CyFalse;
                  uartConfig.flowCtrl = CyFalse;
                  uartConfig.isDma    = CyTrue;
                  status = CyU3PUartSetConfig (&uartConfig, NULL);
              

               

              Regards,

              Noriaki

              • 4. Re: UART on GPIO48/49?
                user_438021184

                With the above I can observe the pin in the signaltap logic analyzer. Looping rx/tx also works. Thank you for your help.