1 Reply Latest reply on Oct 19, 2017 2:32 AM by ndma

    For clock settting by Main PLL clock for FM4

    user_413696083

      Customer is considering their design by S6E2H16F0AGV20000.

       

      They need 160MHz for core clock.

      Form below this datasheet, they are considering below two setting.

      http://www.cypress.com/file/222996/download

       

      #1. input clock 4MHz, (K=1, N=40, M=2)

      #2. input clock 16MHz, (K=1,N=10, M=2)

       

      If both input clock of x'tal are same precision, do you have any differ points between #1 and #2 setting?

      (Which is better?)

       

      Thank you & Regards,

      Masaya

        • 1. Re: For clock settting by Main PLL clock for FM4
          ndma

          Hi Kitahora-san,

           

          Sorry for the delayed response.

          There is no difference in term of satisfying Spec of the datasheet for both settings.

          In terms of which is better, 16 MHz input is preferable.

           

          As 16 MHz reduces the multiplier number, the Band width of the PLL becomes wider, and noise is suppressed, and it becomes advantageous for Jitter characteristics.

           

          Regards,

          Nada